1. Field of the Invention
The present invention relates to chip-on-board assemblies. Particularly, the present invention relates to bare and minimally packaged semiconductor devices which are mountable substantially perpendicularly to a circuit board. Preferably, each of the bond pads of the semiconductor device is disposed proximate a single edge of the semiconductor device. More particularly, the present invention relates to semiconductor devices which include a coating layer over at least a portion of the active surface thereof, which defines notches around the bond pads to impart support to the semiconductor device as it is disposed perpendicularly in relation to the substrate. The present invention also relates to devices for aligning semiconductor devices perpendicularly relative to a circuit board and for establishing electrical connections therebetween.
2. Background of Related Art
The direct attachment of a semiconductor device to a circuit board is known in the art as chip-on-board technology. Semiconductor devices that are directly mountable to a circuit board typically include bond pads adjacent more than one edge thereof or in an area array over the active surface thereof. Methods for attaching semiconductor devices directly to a circuit board include flip-chip technology and tape automated bonding. Typically, when such techniques are employed, a semiconductor device which includes bond pads on an active surface thereof is oriented over the circuit board and substantially parallel thereto in order to establish an electrical connection between the semiconductor device and the circuit board. After connecting such a semiconductor device to a circuit board, a protective coating may be applied over the semiconductor device.
However, the placement of a semiconductor device directly against a circuit board is somewhat undesirable in that, due to the parallel orientation of the semiconductor device relative to the circuit board and the typical placement of the semiconductor device""s active surface against the circuit board, heat must pass through the carrier substrate or the semiconductor device in order to dissipate from the semiconductor device. Thus, the transfer of heat away from the semiconductor device is relatively slow. The horizontal orientation of the semiconductor device also consumes a great deal of area or xe2x80x9creal estatexe2x80x9d on the circuit board. Moreover, chip-on-board attachments are typically permanent, making them somewhat undesirable from the standpoint that they are not readily user-upgradable.
Vertical surface mount packages are also known in the art. When compared with traditional, horizontally mountable semiconductor packages and chip-on-board devices, many vertical surface mount packages have a superior ability to transfer heat away from the semiconductor device. Vertical surface mount packages also consume less area on a circuit board than a horizontally mounted package of the same size. Thus, many skilled individuals in the semiconductor industry are finding vertical surface mount packages more desirable than their traditional, horizontally mountable counterparts.
The following United States patents disclose various exemplary vertical surface mount packages: Pat. No. Re. 34,794, issued to Warren M. Farnworth on Nov. 22, 1994; U.S. Pat. No. 5,444,304, issued to Kouija Hara and Jun Tanabe on Aug. 22, 1995; U.S. Pat. No. 5,450,289, issued to Yooung D. Kweon and Min C. An on Sep. 12, 1995; U.S. Pat. No. 5,451,815, issued to Norio Taniguchi et al. on Sep. 19, 1995; U.S. Pat. No. 5,592,019, issued to Tetsuya Ueda et al. on Jan. 7, 1997; and U.S. Pat. No. 5,635,760, issued to Toru Ishikawa on Jun. 3, 1997.
Many vertical surface mount packages are somewhat undesirable in that they include leads which operatively connect a semiconductor device to a circuit board. The leads of such devices tend to increase the impedance and decrease the overall speed with which such devices conduct electrical signals. Moreover, the packaging of many such devices adds to their undesirability. Typically, packaging requires multiple additional manufacturing steps, which translates into increased production costs. The packaging of many vertical surface mount packages also tends to consume a substantial amount of area or xe2x80x9creal estatexe2x80x9d on the circuit board to which they are attached. However, a prevalent trend in the industry is to increase functionality while consuming less surface area on the circuit board. Further, some semiconductor device packages tend to inhibit the transfer of heat from the semiconductor device contained therein. Moreover, many vertical surface mount packages are not readily user-upgradable.
U.S. Pat. No. 5,593,927 (the xe2x80x9c""927 patentxe2x80x9d), issued to Warren M. Farnworth et al. on Jan. 14, 1997, discloses a method of minimally packaging semiconductor devices which includes forming a protective layer of glass, silicon nitride, silicon dioxide, or polyimide and additional conductive traces on the surface thereof. The thickness of such protective layers is in the range of only about 1 xcexcm to 12.5 xcexcm (xc2xd mil), making them somewhat undesirable. When disposed on vertically mountable semiconductor devices, such protective layers would lend little or no support to the device. Similarly, when placed in a holder such as the one that is disclosed in the ""927 patent, the protective layer is too thin to align electrical connectors of the holder with their corresponding bond pads on the semiconductor device.
Thus, a bare or minimally packaged, low-cost, alignable, vertically mountable semiconductor device which readily attaches to a circuit board is needed. There is also a need for a vertically mountable semiconductor device which is user-upgradable. A vertically mountable semiconductor device is also needed with reduced impedance and improved heat transferability.
The combed vertical mount semiconductor device according to the present invention addresses each of foregoing needs.
The semiconductor device assembly of the present invention includes a semiconductor device having a plurality of bond pads disposed proximate a single edge thereof. At least a portion of the active surface of the semiconductor device is coated with an overcoat layer, which defines a notch around each of the bond pads. Thus, each of the bond pads is exposed. The notches impart the edge of the semiconductor device with a combed appearance. The present invention also includes an alignment device, which attaches to a carrier substrate and includes a receptacle to orient and align the semiconductor device relative to the carrier substrate. Intermediate conductive elements in the receptacle electrically connect each of the bond pads to a corresponding terminal on the carrier substrate. Preferably, upon insertion of the semiconductor device into the alignment device, only a portion of the semiconductor device is disposed within the receptacle.
The present invention also includes a method of forming an overcoat layer on a semiconductor device, wherein the overcoat layer defines notches around the bond pads of a semiconductor device. Methods of designing the semiconductor device of the present invention and securing the semiconductor device to a carrier substrate are also within the scope of the present invention.
Advantages of the present invention will become apparent to those of ordinary skill in the art through a consideration of the appended drawings and the ensuing description.